The present invention relates to information processing apparatus, an information processing methods and programs.
Modern integrated circuits can have not only discrete elements (e.g. transistors) but further comprise photonic components. Electrical test terminals of the discrete elements or of functional groups thereof are as usual located on a surface of a wafer. Such an allocation of the electrical test terminals enables early testing of the integrated circuits. For instance this early testing using the electrical test terminals can be performed before dicing of the wafer in order to ink out the defect dies. After the testing only the chips complying with the specification are processed further (e.g. bonding, packaging, further testing, etc.). Electrical contacting is done as usual by employing electrically conducting needles for connecting an electrical test system with the electrical test terminals. The same electrical test terminals can be further used for bonding.
In contrast, operational photonic terminals used for connecting the chips to external optical waveguides of the package and test photonic terminals of the chips used for optical in-wafer testing are different. The operational photonic terminals are open only after dicing of the chips because they are allocated on sidewalls of the chips. Thus performing optical in-wafer tests requires forming additional test photonic terminals on a wafer surface. As usual they are implemented as an optical coupling segment of an optical waveguide of a chip, wherein the optical coupling segment is covered by a grating enabling optical coupling of an external light source (e.g. a laser) to the optical waveguide of the chip. Forming of such a complex coupling structures on the wafer surface requires not only additional process steps but demands a substantial area of the wafer surface to be sacrificed for these optical couplings. As a result thereof a substantial area is wasted for test structures which are not used for operation of chips after their packaging.